1. Field of the Invention
The present invention relates to an analog-to-digital converter (ADC). More particularly, the present invention relates to an ADC with calibration.
2. Description of Related Art
With the continuous increase of a communication network bandwidth, a conversion speed of a front-end analog-to-digital circuit (ADC) must also be increasingly improved to meet the requirements of an overall system. For example, ultra-wideband (UWB) wireless communication and partial response-maximum likelihood (PRML) need a high-speed sampling clock ADC with 4-6 bits of resolution and low power consumption. Therefore, it is an inevitable trend to develop a high-speed ADC with calibration capability to decrease power consumption.
In a high-speed flash ADC, it is mainly the process variation of a reference ladder resistance and an offset voltage (Vos) caused by an unmatched transistor on a path of a comparator (including a preamplifier and a latch) that influences the accuracy. In order to prevent the comparator from being affected by an input offset voltage, a transistor with a larger aspect ratio is usually required. However, as a result, the parasitic capacitance effect is aggravated, resulting in the limitation to the ADC when operating at a high frequency and thus higher power consumption. In view of this, flash type ADC with a calibration mechanism for saving power consumption will become mainstream in the future.
FIG. 1 is a circuit diagram of calibrating the DC-offset of amplifiers disclosed in US Patent Publication No. U.S. Pat. No. 5,789,974. Referring to FIG. 1, during a calibration process, a negative input terminal of an amplifier is grounded, so an equivalent offset voltage at two input ends of the amplifier is amplified to a logic level via an open loop configuration. Then, the logic value is determined to drive an offset compensation circuit to compensate an offset voltage. The offset voltage of the amplifier can be compensated to the minimum with this technique.
FIG. 2 is a circuit diagram of a comparator-offset compensating converter disclosed in US Patent Publication No. U.S. Pat. No. 5,696,508. Referring to FIG. 2, provided that an offset voltage variation is greater than one least significant bit (1 LSB), during the calibration, after ±3LSB on the reference ladder 12 is switched, the minimum offset on a tap is obtained after comparing with an adjacent tap. This technique is only used to calibrate the offset voltage of ±1LSB, so it is not applicable to high precision ADC compensation.
FIG. 3 is a circuit diagram of an input voltage offset calibration of an analog device using a microcontroller disclosed in US Patent Publication No. U.S. Pat. No. 6,515,464. Referring to FIG. 3, the microcontroller is utilized to send a control code to a calibrate logic and then compensate the offset voltage of an analog device to determine whether an output voltage of an operational amplifier is larger than the voltage of the positive terminal of the comparator. If the output of the comparator transits, the microcontroller calculates the offset voltage of the operational amplifier, and compensates the operational amplifier through the calibrate logic. However, since the comparator has offset voltage, the offset voltage of the operational amplifier cannot be compensated to the minimum by this technique.
FIG. 4 is a circuit diagram of a comparator offset calibration of A/D converters disclosed in US Patent Publication No. U.S. Pat. No. 7,075,465. Referring to FIG. 4, a ramp output by a counter of a calibration control unit is converted by DAC1˜DAC7 to generate calibration voltages V_CAL1˜V_CAL7, so as to calibrate the comparators COMP1˜COMP7. During the calibration, the two input ends of the comparators COMP1˜COMP7 receive reference voltages REF1˜REF7, respectively. In the course of the continuous counting of the counter, when the comparators COMP1˜COMP7 have transition points, the calibration of the transited comparator and the ramp thereof are stopped. This method can be applied to compensate a high precision comparator.
FIG. 5 is a circuit diagram of ADC linearity improvement disclosed in US Patent Publication No. U.S. Pat. No. 6,847,320. A series adjustment resistor is placed between an averaging resistor and a subordinate pre-amplifier. In addition, in calibration, an adjustment current flows through the adjustment resistor to reduce the effect of the offset voltage on the ADC, thereby improving the linearity of the ADC.